Jose Alejandro Galaviz-Aguilar, Ph.D. 📡

Jose Alejandro Galaviz-Aguilar, Ph.D.

RF Research & Development Engineer

Jose Alejandro Galaviz-Aguilar received his M.Sc. (2013) and Ph.D. (2017) degrees in Digital Systems from the Instituto Politecnico Nacional (IPN-CITEDI) in Tijuana, Mexico. During his doctoral studies, he spent two years (2014–2016) as a Visiting Scholar at the RF Nonlinear Research Laboratory, Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, USA, where he gained expertise in RF power amplifier characterization and behavioral modeling.

From October 2024 to December 2025, he served as an RF R&D Engineer at Télécom Paris (France), contributing to the Docte6G national project in collaboration with NXP Semiconductors on the development of advanced digital predistortion techniques for millimeter-wave 6G systems. Prior to this, he held a postdoctoral research appointment at Tecnologico de Monterrey (2020–2024), where he led research initiatives on reconfigurable intelligent surfaces, FPGA-based LDPC encoder/decoder architectures, and spectral optimization strategies for 5G massive MIMO systems.

He is recognized as an IEEE Senior Member and holds a Level I distinction in the Mexican National Researchers System (SNII). His research interests encompass RF power amplifier linearization, digital predistortion, NARMA-based behavioral modeling, FPGA-based digital signal processing, and the application of machine learning to nonlinear RF system design.

Skills

MATLAB / Python

Signal processing, PA modeling, DPD algorithms

FPGA Design

VHDL, Verilog, SystemVerilog, UVM

RF Instrumentation

NVNA, spectrum analyzers, automated testbeds

EDA Tools

Quartus, Xilinx ISE, Keysight ADS, Modelsim

Digital Predistortion

DPD linearization, NARMA, spline modeling

HDL

HDL code generation, fixed-point design, hardware verification

Research & Publication

15+ journal/conference papers, IEEE reviewer

Experience

 
 
 
 
 
RF Research & Development Engineer
October 2024 – December 2025 Palaiseau, Paris, France
  • RF R&D Engineer in the Docte6G national project in collaboration with NXP Semiconductors
  • Developed digital predistortion (DPD) linearization for millimeter-wave (mmW) 6G systems
  • Advanced subband DPD theoretical framework with hardware measurement validation
 
 
 
 
 
Adjunct Researcher (Postdoctoral)
January 2020 – January 2026 Monterrey, Mexico
  • Led reconfigurable intelligent surfaces (RIS) platform with AI-driven algorithms for 5G/6G
  • Designed FPGA-based AWGN module and LDPC encoder/decoder with UVM verification (SAGE Microelectronics)
  • Developed spectral modeling and DPD algorithms for 5G massive MIMO systems
  • Advised 3 M.Sc. students and served on Ph.D. thesis committees
 
 
 
 
 
CONACyT Postdoctoral Fellow
January 2018 – December 2020 Monterrey, Mexico
  • Optimized spectral efficiency in massive MIMO systems for 5G (CONACYT Grant)
  • Designed and implemented DPD algorithms from concept through FPGA prototyping
 
 
 
 
 
Visiting Scholar
January 2014 – December 2016 Columbus, OH, USA
  • RF Nonlinear Research Laboratory, Dept. of Electrical and Computer Engineering
  • Measurement and behavioral modeling of Chireix PA dynamic efficiencies
  • NSF Scholar (2015–2016)

Awards & Distinctions

Researcher Level I (SNII-I)
Distinction by the National Researchers System of Mexico.
IETE JC Bose Memorial Award 2020
Best Engineering Oriented Paper award.
IEEE Senior Member
Recognition as IEEE Senior Member.
Researcher Candidate (SNII)
Distinction by the National Researchers System of Mexico.
CONACyT Postdoctoral Research Fellowship
Two-year postdoctoral research fellowship.
NSF Scholar
National Science Foundation Scholar at The Ohio State University.

Recent Publications

Quickly discover relevant content by filtering publications.
(2025). Field-Programmable Gate Array (FPGA)-Based Lock-In Amplifier System with Signal Enhancement: A Comprehensive Review on the Design for Advanced Measurement Applications. Sensors, vol. 25, no. 2.

DOI

(2024). Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers. IEEE Embedded Systems Letters, vol. 16, no. 3, pp. 307-310.

DOI

(2024). Power Amplifier Modeling Comparison for Highly and Sparse Nonlinear Behavior Based on Regression Tree, Random Forest, and CNN for Wideband Systems. Machine Learning for Complex and Unmanned Systems, CRC Press, Taylor & Francis.

DOI

(2022). A Comparison of Surrogate Behavioral Models for Power Amplifier Linearization under High Sparse Data. Sensors, vol. 22, no. 19, pp. 7461.

DOI

(2022). Reliable comparison for power amplifiers nonlinear behavioral modeling based on regression trees and random forest. 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1527-1530.

DOI

Contact

Feel free to reach out for research collaborations, consulting, or academic inquiries.