Projects | Jose Alejandro Galaviz-Aguilar

Subband Digital Predistortion for 6G Millimeter-Wave Systems

Mon, 01 Dec 2025 00:00:00 +0000

Overview

As an RF R&D Engineer at Télécom Paris (Palaiseau, France), I contributed to the Docte6G national research project in collaboration with NXP Semiconductors, targeting next-generation 6G wireless systems operating at millimeter-wave (mmW) frequencies.

Key Contributions

Developed a subband digital predistortion (DPD) theoretical framework tailored for wideband mmW 6G signals, addressing the unique nonlinear distortion challenges at frequencies above 24 GHz.
Designed and validated DPD algorithms through hardware measurement campaigns, bridging the gap between simulation-based models and real-world PA behavior.
Advanced linearization strategies that account for frequency-dependent memory effects in mmW power amplifiers, improving adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) performance.

Tools & Technologies

MATLAB, Python, Keysight ADS, RF instrumentation (signal generators, spectrum analyzers, NVNA), NXP mmW PA testbeds.

Impact

This work contributes to the foundational RF signal processing layer required for future 6G deployments, where wideband operation at mmW bands demands highly linear and power-efficient transmitter architectures.

FPGA-Based Digital Lock-In Amplifier with Signal Enhancement

Wed, 01 Jan 2025 00:00:00 +0000

Overview

Developed a fully digital lock-in amplifier (LIA) system implemented on FPGA, targeting advanced measurement applications where extracting weak signals buried in noise is critical. This project resulted in two peer-reviewed publications.

Key Contributions

Designed the complete digital signal processing pipeline in VHDL: reference signal generation, phase-sensitive detection, and configurable low-pass filtering stages for in-phase (I) and quadrature (Q) outputs.
Developed a reliable verification methodology combining simulation-based functional verification with quantitative noise analysis, characterizing SNR performance across operating conditions.
Published a comprehensive review of FPGA-based LIA architectures for measurement applications (Sensors, 2025), covering design strategies, signal enhancement techniques, and implementation tradeoffs.
Published the verification and noise analysis methodology in IEEE Embedded Systems Letters (2024), providing a reproducible framework for FPGA-based instrumentation design.

Tools & Technologies

VHDL, Quartus Prime, ModelSim, MATLAB (fixed-point analysis and noise characterization), UVM-based testbenches.

Impact

Lock-in amplifiers are essential instruments in spectroscopy, materials characterization, and sensor readout. This FPGA-based approach enables real-time, low-latency operation suitable for embedded measurement systems where commercial benchtop LIAs are impractical.

FPGA-Based LDPC Encoder/Decoder with UVM Verification

Thu, 01 Jun 2023 00:00:00 +0000

Overview

As part of a collaboration with SAGE Microelectronics at Tecnológico de Monterrey, I designed and verified FPGA-based modules for 5G NR forward error correction (FEC), including an LDPC encoder, decoder, and an additive white Gaussian noise (AWGN) channel emulator for hardware-in-the-loop testing.

Key Contributions

Designed an LDPC encoder supporting 5G NR base graph configurations (BG1/BG2) with configurable code rates and lifting sizes, optimized for throughput on Altera/Intel FPGA platforms.
Implemented a layered min-sum LDPC decoder architecture with early termination, balancing decoding performance against hardware resource utilization.
Developed an FPGA-based AWGN generator module using the Box-Muller method in fixed-point arithmetic, enabling real-time channel emulation for BER testing without external instrumentation.
Built a complete UVM (Universal Verification Methodology) testbench environment in SystemVerilog for functional coverage-driven verification of all codec modules, including scoreboard comparison against golden reference models.

Tools & Technologies

SystemVerilog, UVM, VHDL, Quartus Prime, ModelSim, MATLAB (golden reference and BER analysis), Intel/Altera Cyclone FPGA.

Impact

This project delivered production-quality IP blocks for 5G NR physical layer processing, demonstrating the full RTL-to-verification pipeline from specification through coverage closure.

Spectral Optimization and DPD for 5G Massive MIMO Systems

Sat, 01 Oct 2022 00:00:00 +0000

Overview

During my postdoctoral tenure at Tecnológico de Monterrey (2018–2026), supported by a CONACyT research fellowship, I led the development of DPD algorithms and spectral modeling techniques for 5G massive MIMO transmitter arrays, where per-antenna PA nonlinearity and crosstalk effects degrade system-level spectral efficiency.

Key Contributions

Developed surrogate behavioral models for PA linearization under high sparse data conditions, comparing polynomial, spline, and machine learning approaches (regression trees, random forests, CNNs) for wideband nonlinear modeling.
Designed DPD algorithms optimized for massive MIMO architectures, addressing the challenge of scaling linearization across large antenna arrays while managing computational complexity.
Performed system-level spectral efficiency analysis quantifying the impact of PA nonlinearity on massive MIMO capacity, beam pattern distortion, and adjacent channel interference.
Published results in Sensors (2022), IEEE ISCAS (2022), and contributed a book chapter to Machine Learning for Complex and Unmanned Systems (CRC Press, Taylor & Francis, 2024).
Advised 3 M.Sc. students and served on Ph.D. thesis committees related to this research line.

Tools & Technologies

MATLAB, Python (scikit-learn, TensorFlow), Keysight ADS, RF measurement testbed, statistical modeling frameworks.

Impact

This work bridges classical RF linearization theory with modern machine learning, demonstrating that data-driven surrogate models can match or exceed conventional polynomial DPD approaches — particularly in scenarios with limited or irregularly sampled training data, which is common in multi-band and multi-antenna deployments.

Behavioral Modeling of Chireix Outphasing Power Amplifier

Fri, 01 Dec 2017 00:00:00 +0000

Overview

During my time as a Visiting Scholar (2014–2016) and Ph.D. research at the RF Nonlinear Research Laboratory, Department of Electrical and Computer Engineering, The Ohio State University, I conducted extensive measurement campaigns and behavioral modeling of a Chireix outphasing power amplifier system.

Key Contributions

Performed large-signal dynamic measurements of a Chireix PA using a nonlinear vector network analyzer (NVNA) to capture AM-AM, AM-PM distortion curves and dynamic efficiency behavior under modulated signal excitation.
Developed NARMA-based behavioral models to accurately predict the nonlinear memory effects inherent to outphasing PA architectures, where signal recombination introduces load-dependent distortions.
Validated models against LTE-Advanced waveforms, demonstrating improved prediction accuracy for efficiency and linearity metrics compared to conventional memoryless polynomial approaches.

Tools & Technologies

NVNA (Keysight PNA-X), MATLAB, automated RF testbed, signal generators, spectrum analyzers, Keysight ADS.

Impact

This work formed the core of my Ph.D. dissertation: “Measurement and Behavioral Modeling of Dynamic Efficiencies and Linearization of an LTE-A Chireix PA” (IPN-CITEDI, 2017), and was supported by an NSF Scholarship (2015–2016).