<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Design Verification | Jose Alejandro Galaviz-Aguilar</title><link>https://galaviz-rf.com/tag/design-verification/</link><atom:link href="https://galaviz-rf.com/tag/design-verification/index.xml" rel="self" type="application/rss+xml"/><description>Design Verification</description><generator>Wowchemy (https://wowchemy.com)</generator><language>en-us</language><lastBuildDate>Sat, 01 Jun 2024 00:00:00 +0000</lastBuildDate><image><url>https://galaviz-rf.com/media/icon_huc0a21cd13d3b330e570311c0697204cf_39767_512x512_fill_lanczos_center_3.png</url><title>Design Verification</title><link>https://galaviz-rf.com/tag/design-verification/</link></image><item><title>Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers</title><link>https://galaviz-rf.com/publication/galaviz-2024-fpga-dlia/</link><pubDate>Sat, 01 Jun 2024 00:00:00 +0000</pubDate><guid>https://galaviz-rf.com/publication/galaviz-2024-fpga-dlia/</guid><description/></item></channel></rss>