FPGA | Jose Alejandro Galaviz-Aguilar

Field-Programmable Gate Array (FPGA)-Based Lock-In Amplifier System with Signal Enhancement: A Comprehensive Review on the Design for Advanced Measurement Applications

Wed, 01 Jan 2025 00:00:00 +0000

FPGA-Based Digital Lock-In Amplifier with Signal Enhancement

Wed, 01 Jan 2025 00:00:00 +0000

Overview

Developed a fully digital lock-in amplifier (LIA) system implemented on FPGA, targeting advanced measurement applications where extracting weak signals buried in noise is critical. This project resulted in two peer-reviewed publications.

Key Contributions

Designed the complete digital signal processing pipeline in VHDL: reference signal generation, phase-sensitive detection, and configurable low-pass filtering stages for in-phase (I) and quadrature (Q) outputs.
Developed a reliable verification methodology combining simulation-based functional verification with quantitative noise analysis, characterizing SNR performance across operating conditions.
Published a comprehensive review of FPGA-based LIA architectures for measurement applications (Sensors, 2025), covering design strategies, signal enhancement techniques, and implementation tradeoffs.
Published the verification and noise analysis methodology in IEEE Embedded Systems Letters (2024), providing a reproducible framework for FPGA-based instrumentation design.

Tools & Technologies

VHDL, Quartus Prime, ModelSim, MATLAB (fixed-point analysis and noise characterization), UVM-based testbenches.

Impact

Lock-in amplifiers are essential instruments in spectroscopy, materials characterization, and sensor readout. This FPGA-based approach enables real-time, low-latency operation suitable for embedded measurement systems where commercial benchtop LIAs are impractical.

Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers

Sat, 01 Jun 2024 00:00:00 +0000

FPGA-Based LDPC Encoder/Decoder with UVM Verification

Thu, 01 Jun 2023 00:00:00 +0000

Overview

As part of a collaboration with SAGE Microelectronics at Tecnológico de Monterrey, I designed and verified FPGA-based modules for 5G NR forward error correction (FEC), including an LDPC encoder, decoder, and an additive white Gaussian noise (AWGN) channel emulator for hardware-in-the-loop testing.

Key Contributions

Designed an LDPC encoder supporting 5G NR base graph configurations (BG1/BG2) with configurable code rates and lifting sizes, optimized for throughput on Altera/Intel FPGA platforms.
Implemented a layered min-sum LDPC decoder architecture with early termination, balancing decoding performance against hardware resource utilization.
Developed an FPGA-based AWGN generator module using the Box-Muller method in fixed-point arithmetic, enabling real-time channel emulation for BER testing without external instrumentation.
Built a complete UVM (Universal Verification Methodology) testbench environment in SystemVerilog for functional coverage-driven verification of all codec modules, including scoreboard comparison against golden reference models.

Tools & Technologies

SystemVerilog, UVM, VHDL, Quartus Prime, ModelSim, MATLAB (golden reference and BER analysis), Intel/Altera Cyclone FPGA.

Impact

This project delivered production-quality IP blocks for 5G NR physical layer processing, demonstrating the full RTL-to-verification pipeline from specification through coverage closure.

FPGA-based system for effective IQ imbalance mitigation of RF power amplifiers

Sat, 01 Feb 2020 00:00:00 +0000

Comparison of a genetic programming approach with ANFIS for power amplifier behavioral modeling and FPGA implementation

Mon, 01 Apr 2019 00:00:00 +0000

FPGA Realisation of n-QAM Digital Modulators

Tue, 01 Jan 2019 00:00:00 +0000

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

Sun, 01 Nov 2015 00:00:00 +0000

Modeling memory effects in RF power amplifiers applied to a digital pre-distortion algorithm and emulated on a DSP-FPGA board

Sun, 01 Mar 2015 00:00:00 +0000

Measure-based modeling and FPGA implementation of RF Power Amplifier using a multi-layer perceptron neural network

Sat, 01 Feb 2014 00:00:00 +0000