Field-Programmable Gate Array (FPGA)-Based Lock-In Amplifier System with Signal Enhancement: A Comprehensive Review on the Design for Advanced Measurement Applications

Wed, 01 Jan 2025 00:00:00 +0000

FPGA-Based Digital Lock-In Amplifier with Signal Enhancement

Wed, 01 Jan 2025 00:00:00 +0000

Overview

Developed a fully digital lock-in amplifier (LIA) system implemented on FPGA, targeting advanced measurement applications where extracting weak signals buried in noise is critical. This project resulted in two peer-reviewed publications.

Key Contributions

Designed the complete digital signal processing pipeline in VHDL: reference signal generation, phase-sensitive detection, and configurable low-pass filtering stages for in-phase (I) and quadrature (Q) outputs.
Developed a reliable verification methodology combining simulation-based functional verification with quantitative noise analysis, characterizing SNR performance across operating conditions.
Published a comprehensive review of FPGA-based LIA architectures for measurement applications (Sensors, 2025), covering design strategies, signal enhancement techniques, and implementation tradeoffs.
Published the verification and noise analysis methodology in IEEE Embedded Systems Letters (2024), providing a reproducible framework for FPGA-based instrumentation design.

Tools & Technologies

VHDL, Quartus Prime, ModelSim, MATLAB (fixed-point analysis and noise characterization), UVM-based testbenches.

Impact

Lock-in amplifiers are essential instruments in spectroscopy, materials characterization, and sensor readout. This FPGA-based approach enables real-time, low-latency operation suitable for embedded measurement systems where commercial benchtop LIAs are impractical.

SVM Classifier and evaluation of muscle power of EMG signals and Python implementation

Sun, 01 Nov 2020 00:00:00 +0000